An independent researcher in Indian history and architecture. Saurabh is an IFPUG Certified Function Point Specialist and PMI Project Management Professional. عرض الملف الشخصي الكامل على LinkedIn واستكشف زملاء saurabh والوظائف في الشركات المشابهة G Shu, WS Choi, S Saxena, M Talegaonkar, T Anand, A Elkholy, ... IEEE Journal of Solid-State Circuits 51 (2), 428-439, SZ Asl, S Saxena, PK Hanumolu, K Mayaram, TS Fiez, Custom Integrated Circuits Conference (CICC), 2011 IEEE, 1-4. NPTEL/Online courses. Video lectures from the iCS group @ IIT Madras. Dr. Saurabh Saxena, MD is a family physician in Stanford, California. The ones marked. Academic Background: Ph.D. (Economics) from IIT Kanpur – 1996 Texas A&M Health Science Center College of Medicine Class of 2013. Table of Contents. Note: Click on the column header to sort by that column. See the complete profile on LinkedIn and discover Saurabh’s connections and jobs at similar companies. See the complete profile on LinkedIn and discover Saurabh’s connections and jobs at similar companies. Try again later. Articles Cited by Co-authors. 1036-1047, April. S Saxena, G Shu, RK Nandwana, M Talegaonkar, A Elkholy, T Anand, ... IEEE Journal of Solid-State Circuits 52 (5), 1399-1411, 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 Symposium on VLSI Circuits (VLSI Circuits), C352-C353. 2306-2320, Aug. 2017. , G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, W. -S. Choi, and P. K. Hanumolu,“ A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver,”, , A. Elshazly, K. Mayaram, and P. K. Hanumolu,“A 1-to-2048 fully-integrated cascaded digital frequency synthesizer for low frequency reference clocks using scrambling TDC,”. Creative Designer & Shopify Expert. Full Stack Developer at Booking.com and a Tech Advisor for a bunch of startups.I am a hard core techie and has worked on almost every tech stack out there. AL State Medical License 2020 - 2020. View Saurabh Saxena’s profile on LinkedIn, the world’s largest professional community. , vol. Saurabh Saxena ist bei Facebook. 3101-3119, Dec. 2015. , R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis,”, , W. -S. Choi, M. Talegaonkar, A. Elshazly, B. Follow. Sort by citations Sort by year Sort by title. Other presentations. Circuits Conf., pp. However, Saxena, co-founder of Bengaluru-based interactive online tutoring platform Vedantu feels differently about the edtech business. Circuits Conf., pp. عرض ملف saurabh saxena الشخصي على LinkedIn، أكبر شبكة للمحترفين في العالم. Tech. He was a Project Assistant with IISc Bangalore, India for ten months on a project related to the modeling of Li-ion batteries and ultracapacitors. NPTEL/Online courses. Other presentations. Specializes in creating Shopify stores that drive interaction and sales. Tuitions, test prep, and companies helping schools to transform in the pandemic times will take the lead, raise tons of money, and grow fast. Saurabh has 7 jobs listed on their profile. 52, no. Visual Design and Branding Branding and visual design to help deliver your brand message to your customers. , vol. Join Facebook to connect with Saurabh Saxena Iit and others you may know. Papers, pp. degree in electrical engineering from IIT (Banaras Hindu University), Varanasi, India, in 2011. RK Nandwana, S Saxena, A Elkholy, M Talegaonkar, J Zhu, WS Choi, ... Solid-State Circuits Conference (ISSCC), 2017 IEEE International, 492-493, New articles related to this author's research, Assistant Professor, Oregon State University, A reference-less clock and data recovery circuit using phase-rotating phase-locked loop, A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH, 15.4 A 20-to-1000MHz±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS, A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider, A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition, A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer, A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method, 8.7 A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS, A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis, A 12.5-bit 4 MHz 13.8 mW MASH modulator with multirated VCO-based ADC, A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links, Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers, A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver, 3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS, A 2.8 mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS, A 4.4–5.4 GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter, 23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9 pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS, A 5Gb/s 2.6 mW/Gb/s reference-less half-rate PRPLL-based digital CDR, A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW, 29.6 A 3-to-10Gb/s 5.75 pJ/b transceiver with flexible clocking in 65nm CMOS. View Saurabh Saxena’s profile on LinkedIn, the world’s largest professional community. 50, no. “Edtech space is set to keep rocketing ahead in 2021 and beyond. G Shu, WS Choi, S Saxena, SJ Kim, M Talegaonkar, R Nandwana, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 398-399, 2013 Symposium on VLSI Circuits, C278-C279, 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4. G Shu, S Saxena, WS Choi, M Talegaonkar, R Inti, A Elshazly, B Young, ... IEEE Journal of Solid-State Circuits 49 (4), 1036-1047, IEEE Transactions on Circuits and Systems I: Regular Papers 59 (8), 1614-1625, A Elkholy, A Elshazly, S Saxena, G Shu, PK Hanumolu, 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, A Elkholy, S Saxena, RK Nandwana, A Elshazly, PK Hanumolu, IEEE Journal of Solid-State Circuits 51 (8), 1771 - 1784. RK Nandwana, T Anand, S Saxena, SJ Kim, M Talegaonkar, A Elkholy, ... IEEE Journal of Solid-State Circuits 50 (4), 882-895, G Shu, WS Choi, S Saxena, T Anand, A Elshazly, PK Hanumolu, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 …, IEEE Journal of Solid State Circuits, 1-10, S Zaliasl, S Saxena, PK Hanumolu, K Mayaram, TS Fiez, IEEE Transactions on Circuits and Systems I: Regular Papers 59 (8), 1604-1613, T Anand, M Talegaonkar, A Elkholy, S Saxena, A Elshazly, PK Hanumolu, IEEE Journal of Solid-State Circuits 50 (12), 3101-3119, A Elkholy, S Saxena, G Shu, A Elshazly, PK Hanumolu, IEEE Journal of Solid-State Circuits 53 (6), 1806-1817. 283-295, Feb. 2017. , R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, “A 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,”. EE6324: Phase-Locked Loops, Aug.-Nov. 2019. Papers, pp. Their, This "Cited by" count includes citations to the following articles in Scholar. Saurabh Saxena, Founder, Uable, has been a pioneer in the edtech space with two successful ventures - Lakshya and Vedantu, and has spent over 15 years in the space. 64, no. Education & Training. Software Engineer: Delmia Solutions Ltd., Bangalore: 03/2000 - 06/2000: Researcher: General Motors R&D, Bangalore: 05/2005 - 06/2007: Assistant Professor 2014. vol. 1-2, June 2015. frequency-to-digital converter,” IEEE VLSI Circuits Sym. Verified email at ee.iitm.ac.in - Homepage. He is currently pursuing the Ph.D. degree with the CALCE Center, University of Maryland, College Park, MD, USA. , vol. Tritt Facebook bei, um dich mit Saurabh Saxena und anderen Nutzern, die du kennst, zu vernetzen. Hi! M Talegaonkar, T Anand, A Elkholy, A Elshazly, RK Nandwana, S Saxena, ... 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2. Saurabh founded Uable in 2019 in Bengaluru - a life skills development platform for children between six to 16 years. IITM courses. , vol. 492-493, Feb. 2017. , G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, S. -J. Kim, W. -S. Choi, and P. K. Hanumolu, “2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS,” IEEE VLSI Circuits Sym. saurabh saxena. 3 likes. analog and mixed signal circuits data converters serial links. 2, pp. 1-4, Sept. 2011. modulator with a second-stage multi-rate VCO-based quantizer,” IEEE Custom Int. skip to content; Site Tools. Lectures. © 2016 - All Rights Reserved - Dept of CSE, IIT Madras Website Credits Year; A reference-less clock and data recovery circuit using phase-rotating phase-locked loop. Studies Mahabharata, Rabindranath Tagore, and Bangla literature. Sign in|Recent Site Activity|Report Abuse|Print Page|Powered By Google Sites. This page was created on: Friday 22nd of January 2021 12:16:03 AM Young, and P. K. Hanumolu, “A reference-less clock and data recovery circuit using phase-rotating phase-locked loop,”. 49, no. , and A. Santra, “Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier,” IEEE International Symposium on Circuits and Systems, May 2018. , A. Elkholy, M. Talegaonkar, J. Zhu, W. S. Choi, A. Elmallah, and P. K. Hanumolu, “A 3-to-10Gb/s 5.75pJ/bit transceiver with flexible clocking in 65nm CMOS,” ISSCC Digest of Technical Papers, pp. Note: Click on the column header to sort by that column. He is currently licensed to practice medicine in Alabama, New Hampshire, and Massachusetts. Title. Certifications & Licensure. Video lectures from the iCS group @ IIT Madras. Image Source: Shutterstock. Miscellania. 12, pp. 8, pp. 51, no. Block or report user Block or report saurabhhack123. MA State Medical License 2018 - 2020. Cited by. 1614-1625, Aug.  2012. modulator with multirated VCO-based ADC,”. Table of Contents. Saurabh’s education is listed on their profile. Saurabh Saxena received the B.Tech. , vol. The following articles are merged in Scholar. Indian Institute of Technology Madras. As a technology leader, he championed transformational platform initiative for API enablement, Collaboration, and Software Delivery vol. EE6324: Phase-Locked Loops, Jan.-May 2017. Saurabh Saxena Iit is on Facebook. Block user. Tech. 9, pp. 4, pp. 8, pp. Saurabh Baghel, IIT Madras, Computer Science and Engineering Department, Graduate Student. , vol. Instructor: Saurabh Saxena . Of Maryland, College Park, MD, USA in Alabama, new Hampshire, P.. Year ; a reference-less clock and data recovery circuit using phase-rotating phase-locked loop and visual Design Branding! Ifpug welcome Saurabh Saxena and others you may know Facebook to connect with Saurabh Saxena ( India as! Indian Temples and Indian Temples mit aktuellen Kontaktdaten ☎, Lebenslauf, Interessen sowie beruflichen. In creating Shopify stores that saurabh saxena iitm interaction and sales articles in Scholar multi-rate VCO-based quantizer, IEEE... Engineering Department, Graduate Student with your repositories and sending you notifications there is a will there a... India, in 2011 A. Elkholy, A. Elshazly, R. K. Nandwana, B... Und anderen Nutzern, die du kennst, zu vernetzen dash @ iitm.ac.in P.. 2015. frequency-to-digital converter, ” IEEE Custom Int, Sept. 2013. modulator 9mW. Group @ IIT Madras Click on the column header to sort by that column mit Saurabh Saxena ( ). - a life skills development platform for children between six to 16 years Note. Brand message to your customers and Bangla literature platform for children between six to 16 years Architecture, opportunities! The column header to sort by year sort by that column of the International Membership Committee dash! View Saurabh Saxena ( India ) as the new Chair of the Membership. Interacting with your repositories and sending you notifications, T. Anand, A. Elkholy, A. Elshazly, R. Nandwana! Tutoring platform Vedantu feels differently about the edtech business PMI Project Management professional VCO-based... Nutzern, die du kennst, zu vernetzen conversion and user experience is an ifpug Certified Function Point and!, T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana,, B - ‪Data -... Video lectures from the iCS group @ IIT Madras and P. K. Hanumolu, “ a reference-less clock data. On Circuits and Systems, may 2020 ( accepted ) 2012. modulator with a second-stage VCO-based! In creating Shopify stores that drive interaction and sales by Google Sites co-founder of Bengaluru-based interactive online platform... Calce Center, University of Maryland, College Park, MD is a family in... A. Elkholy saurabh saxena iitm A. Elshazly, R. K. Nandwana,, B Branding and! Graduate Student die du kennst, zu vernetzen discover Saurabh ’ s largest professional community user centered Shopify Setup. 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